Keren Zhu

While AI fuels exponential growth in computational demands, the traditional digital-centric electronic design automation (EDA) process has become an environmental liability: today's data centers alone consume 1.5% of global electricity.

Keren Zhu employs AI-driven physical synthesis to transform EDA from a digital-only constraint into an innovation catalyst, automating custom circuit design to enable next-generation energy-proportional computing architectures, from analog neural interfaces to in-memory systems. He developed a suite of AI-driven design methodologies and open-source tools, including MAGICAL, the first silicon-proven open-source automated analog layout system. It achieves full Spice-to-GDSII automation and was demonstrated through a successful TSMC 40nm tapeout, where a synthesized ΔΣ ADC achieved an SNDR of 68.2dB.

He fused graph neural networks with constraint optimization to propose GeniusRoute, a routing paradigm based on generative neural networks that reduces wirelength by 22.8% compared to conventional approaches. He also developed a hierarchical layout synthesis framework based on Bayesian optimization, significantly enhancing design efficiency. Additionally, he developed a GNN-based automatic extraction method for circuit symmetry constraints, solving the challenge of generating matching constraints in analog circuit layout. These technologies have been adopted by Synopsys and Nvidia EDA tools.

He further extended his work to physical-logic co-design, developing the PigMap framework, which introduces preemptive physical awareness into the logic stage and achieves a 13.4% PPA gain on EPFL benchmarks. He also introduced a logic synthesis method guided by Monte Carlo tree search, which yielded an 8.74% area reduction with a 1.24x speedup. These approaches effectively bridge the disconnect between logic synthesis and physical design in traditional EDA workflows.

In recent years, his team's research has expanded to enable emerging computing paradigms, including automated layout generation for in-memory computing architectures, curvature-aware routing algorithms for photonic integrated circuits, and development of a 2.5D/3D-IC toolflow, demonstrating EDA technology's adaptability across diverse computing architectures.