Kaiming Cai

SOT-MRAM offers key advantages such as high speed, low energy consumption, and exceptional endurance, making it one of the most promising non-volatile memory solutions to replace traditional cache memory in the post-Moore era. Once mass production is achieved, it is expected to play a critical role in areas such as artificial intelligence, cloud computing, and the Internet of Things, potentially setting a new industry standard for next-generation memory technologies.

Globally, this technology is still in the early stages of industrialization and faces several challenges, including high-density integration, field-free switching, and reliable fabrication processes. To accelerate its industrial adoption, Kaiming Cai focuses on overcoming performance degradation issues associated with field-free integration schemes, such as reduced integration density, decreased write efficiency, and increased error rates.

To address these issues, he proposed the concept of multi-pillar SOT-MRAM, enabling lower write current and higher integration density. This design significantly enhances the density and energy efficiency of SOT-MRAM. Moreover, through experimentation, he was the first to demonstrate ultrafast field-free switching in multi-pillar SOT-MRAM. The current pulse required was as low as 0.3 nanoseconds, with power consumption reaching just 60 femtojoules per bit.

Kaiming also proposed a device structure of scaled perpendicular SOT-MRAM, which achieved substantial performance improvements. This design effectively minimized the bit cell area, reduced power consumption by 63%, and extended device endurance beyond 10¹⁵ cycles. Through systematic studies on device scaling, he demonstrated the critical role of device scaling in enhancing device performance.

During his tenure as a Senior Researcher at IMEC, a leading international research institute, he leveraged these technological breakthroughs to lead the development of third-generation magnetic chip and devices, and successfully demonstrated the CMOS-integrated SOT-MRAM devices on 300mm wafers for high-performance computing.

These achievements have laid the foundation for the large-scale industrialization of SOT-MRAM.